Delta-sigma analog-to-digital converters, also known as sigma-delta analog-to-digital converters, are used to provide high resolution data conversion. A typical first order delta-sigma analog-to-digital converter (ADC) is illustrated in FIG. 1. It comprises an ADC input 310 for an analog input signal and an ADC output 350 for a digital output signal. The ADC input 310 is coupled to a first input of a summing stage 320, and an output of the summing stage 320 is coupled to an input of an integrator 330. An output of the integrator 330 is coupled to an input of an analog-to-digital conversion stage 340, denoted A/D in FIG. 1, and an output of the analog-to-digital conversion stage 340 is coupled to the ADC output 350. A digital-to-analog conversion stage 360 is coupled in a feedback path between the ADC output 350 and a second input of the summing stage 320. More specifically, the digital-to-analog conversion stage 360 has an input coupled to the ADC output 350 and an output coupled to the second input of the summing stage 320 for delivering a feedback signal. The second input of the summing stage 320 is an inverting input, and therefore the output of the summing stage 320 delivers to the input of the integrator 330 the difference between the analog input signal and the feedback signal, known as an error signal. For a one-bit ADC, the analog-to-digital conversion stage 340 can comprise a limiter for generating the digital output signal as a binary signal indicative of whether the signal at the output of the integrator 330 is above or below a threshold. For a one-bit ADC, the digital-to-analog conversion stage 360 can comprise a switch 365 controlled by the digital output signal and delivering to the second input of the summing stage 320 either of two reference voltages, VREF+ and VREF−, according to the binary value of the digital output signal. The portion of the feedback path from the digital-to-analog conversion stage 360 to the second input of the summing stage 320 may be referred to as the reference voltage path.
A typical third order feed forward delta-sigma ADC is illustrated in FIG. 2, with components similar to those of the first order delta-sigma ADC illustrated in FIG. 1 having the same reference numerals. The third order feed forward delta-sigma ADC comprises the ADC input 310 for the analog input signal and the ADC output 350 for the digital output signal. The ADC input 310 is coupled to the first input of the summing stage 320 via a first amplification stage 315 having a gain g1, and an output of the summing stage 320 is coupled to an input of a first integrator 330a. An output of the first integrator 330a is coupled to an input of a second integrator 330b having a gain g2, and an output of the second integrator 330b is coupled to an input of a third integrator 330c having a gain g3. Outputs of the first, second and third integrators 330a, 330b, 330c are coupled to respective inputs of a combining stage 316 via respective second, third and fourth amplification stages 331a, 331b and 331c having respective summing coefficients s1, s2 and s3. An output of the combining stage 316 is coupled to an input of the analog-to-digital conversion stage 340, and an output of the analog-to-digital conversion stage 340 is coupled to the ADC output 350. The analog-to-digital conversion stage 340 can comprise a limiter for generating the digital output signal as a binary signal indicative of whether the signal at the output of the combining stage 316 is above or below a threshold Qn. The feedback path comprising the digital-to-analog conversion stage 360 is coupled between the ADC output 350 and a second input of the summing stage 320 for delivering the feedback signal. The digital-to-analog conversion stage 360 has a gain gref, also referred to as the gref coefficient. The second input of the summing stage 320 is an inverting input, and therefore the output of the summing stage 320 delivers to the input of the first integrator 330a the difference between the analog input signal and the feedback signal. The principles of operation of the third order delta-sigma ADC illustrated in FIG. 2 are well documented and will not be repeated here.
There is a requirement to vary the gain of a delta-sigma ADC, in particular to provide low noise data conversion for analog input signals of different amplitudes. Controlling the gain in a delta sigma ADC may be done by acting on the feedback path and tuning the fraction of a reference voltage which is subtracted from the analog input signal to determine the error signal. Some solutions implement gain control of the signal path using a programmable gain amplifier, which will set the input to the delta sigma ADC to the desired amplitude. Therefore, one way of providing gain control is to provide a switchable gain amplifier between the ADC input 310 and the first input of the summing stage 320. However, switching the gain in steps can introduce distortion to the analog input signal undergoing analog-to-digital conversion. For example, audible artefacts may be introduced into an audio signal.
The disclosure relates to improvements in analog-to-digital conversion.